A phase-locked loop (hereinafter, PLL) is a feedback system that compares output phase and input phase to achieve frequency lock, and PLLs are widely used in many communication systems. FIG. 1 is a diagram of a PLL circuit. The PLL circuit 10 includes a phase detector 13, a loop filter 15, a voltage controlled oscillator (hereinafter, VCO) 17, and a divider 19.
In the PLL circuit 10, an input signal and a feedback signal are input to the phase detector 13 which determines a phase difference between these two signals. As shown in FIG. 1, the input signal can be a reference clock clkref provided by a reference clock generator 11. This phase difference is converted to a control voltage through the loop filter 15. The VCO 17 varies its output frequency in accordance with the control voltage. The output signal of the VCO 17 is divided by the divider 19 to obtain the feedback signal. Then, the feedback signal is fed to the phase detector 13 and compared with the input signal. The phase detector 13 generates the phase difference again. The PLL circuit 10 will track and eventually be locked in frequency and phase within stability.
Phase noise (hereinafter, PN) is a parameter commonly used to describe noise performance of oscillators and is a measure of the power spectral density of the phase angle. Moreover, phase noise in frequency domain is equivalent to jitter in time domain. According to simulation results of integrated phase noise (hereinafter, IPN) of the PLL circuit 10, the reference clock generator 11 is one of the noise sources of phase noise. Therefore, lowering phase noise of the reference clock generator 11 is important for PLL circuit 10.
Generally, lowering the phase noise results in an amplitude loss in the reference clock generator 11, and the amplitude loss may infer that the signal-to-noise ratio (hereinafter, SNR) decreases. The SNR represents the comparison between the level of a desired signal to the level of background noise, and the higher SNR is preferred. Alternatively speaking, the amplitude loss accompanied with lowering the phase noise may worsen the SNR.
Both the phase noise and the amplitude loss are important design metrics for the reference clock generator 11, but implementation of decreasing the phase noise and lowering the amplitude loss are contradictory to each other. Consequentially, design of the reference clock generator 11 becomes a dilemma.